1. Field of the Invention
The present invention relates to an error correction device, and, more specifically, to an error correction device storing a corrected data in a data buffer composed of a plurality of storage areas.
2. Description of Related Art
Development of a recording media having high capacity has recently been accelerated due to the Blu-ray standard and HD DVD (High-Definition Digital Versatile Disc) standard. In some DVD disc devices, there is a need to process a large amount of data at high speed. For example, a configuration in which a technique disclosed in Japanese Unexamined Patent Application Publication No. 2001-143408 is applied to a DVD/CD (Digital Versatile Disc/Compact Disc) disc device will be shown in FIGS. 3 and 4. FIG. 5 shows a data format of ECC (error check and correct) block of the DVD.
FIG. 3 is a block diagram showing an example of an overall structure of the DVD/CD disc device according to a background art. Data processing when the DVD disc is reproduced will be described hereinafter. As shown in FIG. 3, a DVD/CD disc device 200 includes a CPU (Central Processing Unit) 202, a pickup 203, a read/write channel 204, a HOST I/F 206, a buffer control circuit 207, a format control circuit 208, a data buffer 209, and an error correction circuit 300.
The CPU 202 controls the whole DVD/CD disc device. The pickup 203 reads data (uncorrected data) from the DVD disc and transmits the data to the read/write channel 204. The read/write channel 204 demodulates the data and transmits the data to the format control circuit 208. The format control circuit 208 processes the data according to the disc format that is different between discs. The data that is processed at the format control circuit 208 is transmitted to the error correction circuit 300.
In DVD for example, the data is processed to have 182 bytes*208 rows, as shown in FIG. 5. The data having 182 bytes*208 rows is called ECC block and the error correction process of the DVD is performed in this ECC block unit. The data from 173-rd byte to 182-nd byte of each row is called PI and the data from 193-rd row to 208-th row of the ECC block is called PO. PO and PI are called ECC code and the data from 172 bytes*192 rows, which is the data excluding the ECC code, is main data.
The HOST I/F 206 uses the corrected data. The HOST I/F 206 accesses the corrected data stored in the data buffer 209 through the buffer control circuit 207.
The buffer control circuit 207 is the circuit controlling reading/writing the data from/to the data buffer 209.
The data buffer 209 is configured by SDRAM (Synchronous Dynamic Random Access Memory) (for example EDS1216AGTA: made by Elpida Memory, Inc). The data buffer 209 temporarily stores the data which is now being corrected and has a capacity of 128 megabytes. Note that the SDRAM is composed of a plurality of storage areas called page and continuous access is possible in the same page, which makes it possible to improve process speed.
The error correction circuit 300 includes a PI correction circuit 301, a decoder 302, and a restoration part 303.
The PI correction circuit 301 is the circuit that performs a first correction in a PI direction (182 bytes in one row) shown in FIG. 5 by one row unit.
The decoder 302 is the circuit generating error correction code and error position information of the error data in the ECC block. The error correction code is described in “The Illustrated DVD Reader, Chapter 3.2.5 Decoding of Error Correction Code”, Ohmsha, Ltd., ISBN 4-274-03606-5, p. 106-109.
The restoration part 303 is the circuit for rewriting data stored in the data buffer 209 according to the generated error position information and error correction code.
Now, a operation of the error correction circuit 300 according to the background art will be described with reference to FIG. 4. FIG. 4 is a block diagram showing one example of a configuration of the error correction circuit according to the background art. The error correction circuit 300 shown in FIG. 4 includes the PI correction circuit 301, the decoder 302, and a restoration part 307.
The data processed by the format control circuit 208 is input to the PI correction circuit 301. The PI correction circuit 301 performs the first correction in the PI direction (182 bytes in one row) by one row unit. The PI direction is shown in the data format of the ECC block of the DVD in FIG. 5. Then the PI correction circuit 301 transmits the data excluding the ECC code to the data buffer 209 through the buffer control circuit 207 by ECC block unit (1ECC).
The number of pages needed to store the data for 1ECC in the data buffer 209 can be calculated by dividing the data for 1ECC by the number of bytes in one page. Specifically, the data length excluding the ECC code is 172 bytes*192 rows and capacity for one page is 1024 bytes. Therefore, the number of pages is 33 pages as shown in equation 1.172 bytes*192 rows/1024 bytes=32.24 pages  (eq. 1)
One buffer for PO correction and one buffer for PI correction are allocated to one page on the data buffer 209 to facilitate transferring of the data to the SDRAM. Therefore, the buffers for PO correction 309-1 to 309-33 and the buffers for PI correction 312-1 to 312-33 are needed to be provided for 1ECC.
The data on which the first correction is performed by the PI correction circuit 301 is also transmitted to the decoder 302 by ECC block unit. The transmitted data includes the ECC code. The decoder 302 includes a PO operation circuit 310, a PI operation circuit 304, and an error polynomial operation circuit 320.
The PO operation circuit 310 performs a syndrome calculation in a PO direction (192 rows in a vertical direction) shown in FIG. 5 on each column of the input ECC block and stores the calculation result for 182 columns. After the PO syndrome calculation for 1ECC is completed, the PO operation circuit 310 transmits the calculated data to the error polynomial operation circuit 320. The error polynomial operation circuit 320 generates the error position information and the error correction code.
The PI operation circuit 304 performs the syndrome calculation in the PI direction (182 bytes in a horizontal direction) shown in FIG. 5 on each row of the input ECC block and stores the calculation result for 192 rows for a second PI correction process. The error correction code and the error position information in the ECC block generated by the error polynomial operation circuit 320 are transmitted to an error address operation selection circuit 305 in the restoration part 307.
The restoration part 307 includes the error address operation selection circuit 305, a page size register 306, an address offset register 308, buffers for PO correction 309-1 to 309-33, buffers for PI correction 312-1 to 312-33, an EXOR circuit 317, a buffer for corrected data 316, and a buffer access control circuit 315.
The page size register 306 stores the data indicating one page size of the data buffer 209.
The address offset register 308 stores the address on the data buffer 209, which is the leading address of the corrected data that is to be processed.
The error address operation selection circuit 305 determines where in the buffers for PO correction 309-1 to 309-33 the error position information in 1ECC block is stored based on the data of the address offset register 308 and the data of the page size register 306. Then the error address operation selection circuit 305 stores the error correction code and the address on the data buffer 209 in which the corresponding data is stored in the buffers for PO correction 309-1 to 309-33. The restoration part 307 stores the error correction code for 1ECC and the address on the data buffer 209 in the buffers for PO correction 309-1 to 309-33. Then the restoration part 307 rewrites the data stored in the data buffer 209.
The restoration part 307 reads out the address on the data buffer 209 stored in the buffer for PO correction 309-1 and reads out the data of the data buffer 209 designated by the address. The exclusive-OR operation is performed on the data that is read out and the error correction code data held by the buffer for PO correction 309-1 by the EXOR circuit 317 and the operation result is stored in the buffer for corrected data 316. After all the data held by the buffer for PO correction 309-1 are processed, the restoration part 307 writes back the data stored in the buffer for corrected data 316 to the data buffer 209.
After writing back the data, the restoration part 307 successively performs the same process on the buffers for PO correction 309-2 to 309-33. When processing of 33 buffers for PO correction has completed, the error correction in the PO direction for 1ECC is completed. The restoration part 307 performs the error correction in the PI direction again after the error correction in the PO direction is completed.
When the PO corrected data is written back to the data buffer 209, the corrected data is also transmitted to the PI operation circuit 304. The PI operation circuit 304 compensates the operation result stored in the PI operation circuit 304 based on the PO corrected data. After all the operation result is compensated, the PI operation circuit 304 transmits the corrected syndrome calculation result to the error polynomial operation circuit 320. Then the error polynomial operation circuit 320 generates the error correction code and the error position information in 1ECC block. The generated error correction code and the error position information in 1ECC block are transmitted to the error address operation selection circuit 305.
The error address operation selection circuit 305 determines where in the buffers for PI correction 312-1 to 312-33 the error position information in 1ECC block is stored based on the data of the address offset register 308 and the data of the page size register 306. Then the error address operation selection circuit 305 stores the error correction code and the address on the data buffer 209 in which the corresponding data is stored in the buffers for PI correction 312-1 to 312-33.
Then the restoration part 307 rewrites the data stored in the data buffer 209. The address on the data buffer 209 stored in the buffer for PI correction 312-1 is read out and the data of the data buffer 209 designated by the address is read out. The exclusive-OR operation is performed on the data that is read out and the error correction code data stored in the buffer for PI correction 312-1 by the EXOR circuit 317. The operation result is stored in the buffer for corrected data 316. After all the data stored in the buffer for PI correction 312-1 are processed, the data stored in the buffer for corrected data 316 is written back to the data buffer 209.
After writing back the data, the restoration part 307 successively performs the same process on the buffers for PI correction 312-2 to 312-33. When processing of 33 buffers for PI correction has completed, the error correction in the PI direction is completed. The error correction process of the data of 1ECC block is thus completed.
Now, a data flow will be described with reference to FIG. 6. FIG. 6 is a timing chart of the error correction process according to the background art. T0 to T5 indicate time. After PI correction is performed on the data input from the format control circuit 208 to the PI correction circuit 301, the PI corrected data is transmitted to the PO operation circuit 310, the PI operation circuit 304, and the buffer control circuit 207 (401, 402, 403). After the data for 1ECC is transmitted, the operation result obtained from the PO operation circuit 310 is input to the error polynomial operation circuit 320 (404). The error correction code and the error position information in 1ECC block generated at the error polynomial operation circuit 320 are input to the error address operation selection circuit 305 (405).
It is determined by the error address operation selection circuit 305 where in the buffers for PO correction 309-1 to 309-33 the error position information and the error correction code are stored. Then the error position information and the error correction code are stored in the determined buffer for PO correction (406). When the error position information for 1ECC is stored in the buffers for PO correction 309-1 to 309-33, the restoration part 307 reads out the error correction code and the address on the data buffer 209 successively from the buffer for PO correction 309-1 and rewrites the data stored in the data buffer 209 through a data buffer rewriting bus (buffer control circuit 207) (407). The rewritten data is also transmitted to the PI operation circuit 304 (408).
The operation result is compensated using the rewritten data in the PI operation circuit 304. When the rewriting of the buffers for PO correction 309-1 to 309-33 is completed, the PI operation circuit 304 inputs the compensated operation result to the error polynomial operation circuit 320 (409). The error correction code and the error position information in the 1ECC block generated at the error polynomial operation circuit 320 are input to the error address operation selection circuit 305. It is determined by the error address operation selection circuit 305 where in the buffers for PI correction 312-1 to 312-33 the error position information and the error correction code are stored. Then the error position information and the error correction code are stored in the determined buffer for PI correction (410).
When the error position information for 1ECC is stored in the buffers for PI correction 312-1 to 312-33, the error correction code and the address on the data buffer 209 are read out successively from the buffer for PI correction 312-1 and the data stored in the data buffer 209 is rewritten (411). When rewriting of the data stored in the data buffer 209 is completed to the buffer for PI correction 312-33, the correction process for 1ECC is completed.
The PI correction process for the last data is completed when the process for rewriting of the data buffer 209 for 33 pages is completed (413) after the last error position information and the error correction code are transmitted from the error polynomial operation circuit 320 (412).
However, in the background art, the data held by the data buffer 209 is rewritten after the error detection process for 1ECC is completed and after the error correction code and the address on the data buffer 209 indicating the error correction code are stored in the buffers for PO correction 309-1 to 309-33 and the buffers for PI correction 312-1 to 312-33. Further, in rewriting the data held by the data buffer 209, the data is written back to the data buffer 209 after being stored in the dedicated buffer for corrected data 316 when the data, obtained by performing exclusive-OR operation on the data held by the buffers for PO correction 309-1 to 309-33 or the buffers for PI correction 312-1 to 312-33 (error correction code) and the data held by the data buffer 209 (data that is to be corrected), is temporarily stored.
Therefore, 33 buffers for PO correction and the 33 buffers for PI correction are needed to store the error data for 1ECC. The dedicated buffer for corrected data 316 is also needed. Therefore, the area of the error correction circuit 300 is large in the background art. In the background error correction circuit, the buffer capacity needed for error correction process and the area of the error correction circuit are large.